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--- instruction_encoding [2023/11/15 15:26] – [Jump instructions] pulkomandy
+++ instruction_encoding [2024/06/28 20:37] – [ALU instructions] simer
@@ Line 7: / Line 7: @@
 ^Contents|Opcode0|Operand A|Opcode1|6-bit Immediate         ||
+===== Summary =====
+^Opcode 0\1     ^ 0       ^ 1            ^ 2           ^ 3  ^ 4                        ^ 5        ^ 6        ^ 7     ^
+^Addressing mode|[BP+Imm6]|#Imm6         |             |[Rs]|Rs,#Imm16,[Addr16], Rs ASR|Rs LSL/LSR|Rs ROL/ROR|[Addr6]|
+^       0  | **ADD**, //JB, JNAE, JCC// ||             | **ADD** |||||
+^       1  | **ADC**, //JAE, JNB, JCS// ||             | **ADC** |||||
+^       2  | **SUB**, //JGE, JNL, JSC// ||             | **SUB** |||||
+^       3  | **SBC**, //JL, JNGE, JSS// ||             | **SBC** |||||
+^       4  | **CMP**, //JNE, JNZ//      ||             | **CMP** |||||
+^       5  | //JE, JZ//                 ||                       ||||||
+^       6  | **NEG**, //JPL//           ||             | **NEG** |||||
+^       7  | //JMI//                    ||                       ||||||
+^       8  | **XOR**, //JBE, JNA//      ||             | **XOR** |||||
+^       9  | **LD**, //JA, JNBE//       ||POP,RETF,RETI| **LD**  |||||
+^       A  | **OR**, //JLE, JNG//       ||             | **OR**  |||||
+^       B  | **AND**, //JG, JNLE//      ||             | **AND** |||||
+^       C  | **TEST**, //JVC//          ||             | **TEST**|||||
+^       D  | **ST**, //JVS//            ||PUSH         | **ST**  |||||
+^       E  | //JMP//                    ||             ||||||
+^       F  | MUL.us        |CALL         |MAC.us,//GOTO// | MAC.us |MUL.ss|INT,IRQ,FIR_MOV,BREAK|MAC.ss ||
+  * Instructions in bold: uses the addressing mode listed on the first line
+  * Instructions in italics: only if operand A (destination register) is PC
 ===== Special instructions =====
@@ Line 114: / Line 137: @@
 ^%% D:[++Rs]      %%| ALU op|  Op. A  | 3       | 7                | Rs      |
 ^%% Rs            %%| ALU op|  Op. A  | 4       | 0                | Rs      |
-^%% #Imm16        %%| ALU op|  Op. A  | 4       | 1                | Rs      | |16-bit immediate in next word|
+^%% #Imm16        %%| ALU op|  Op. A  | 4       | 1                | Rs*     | |16-bit immediate in next word, Rs is first operand|
-^%% From [Addr16] %%| ALU op|  Op. A  | 4       | 2                | Rs      | |16-bit address in next word|
+^%% From [Addr16] %%| ALU op|  Op. A  | 4       | 2                | Rs*     | |16-bit address in next word, Rs is first operand|
-^%% To [Addr16]   %%| ALU op|  Op. A  | 4       | 3                | Rs      | |16-bit address in next word|
+^%% To [Addr16]   %%| ALU op|  Op. A  | 4       | 3                | Rs*     | |16-bit address in next word, Rs is first operand|
 ^%% Rs ASR shift  %%| ALU op|  Op. A  | 4       | 4 + (shift - 1)  | Rs      |
 ^%% Rs LSL shift  %%| ALU op|  Op. A  | 5       | shift - 1        | Rs      |
@@ Line 137: / Line 160: @@
 The ST operation uses the second source operand (Rs, address, ...) as the target, and operand A (always a register) as the source.
+Other operations can use both forms, so the "From [Addr16]" would be something like this:
+''R3 = R2 + [Addr16]''
+and the "To [Addr16]" corresponds to:
+''[Addr16] = R2 + R3''
+(so in this case the register encoded in OPA is used as a source, not a destination).
+The LD and ST operations with the 16-bit addressing mode ignore the value of Rs, they use only Ra and the 16-bit value.