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Table of Contents
The instructions are 16 bit words. Most instructions use a single word, however, some of them use a second word to store an immediate 16-bit value.
The general format is as follows:
| Bits | 15-12 | 11-9 | 8-6 | 5-3 | 2-0 |
|---|---|---|---|---|---|
| Contents | Opcode0 | Operand A | Opcode1 | OPN | Operand B |
| Contents | Opcode0 | Operand A | Opcode1 | 6-bit Immediate | |
Special instructions
“Special” instructions are identified by Opcode0 = 0xF
BREAK is probably somewhere here, document it.
Multiplication
| Instruction | Opcode0 | Operand A | Opcode1 | OPN | Operand B |
|---|---|---|---|---|---|
| MUL (unsigned) | F | Op.A | 0 | 1 | Op.B |
| MUL (signed) | F | Op.A | 4 | 1 | Op.B |
- document possible values for OPN
- document MAC instructions
- document unsigned-to-unsigned vs signed-to-unsigned instructions
- division instructions may have a similar format
Note: Operand A cannot be 7 (it is not possible to multiply PC with something).
CALL and GOTO
| Instruction | Opcode0 | Operand A | Opcode1 | 6-bit Immediate | Second word | |
|---|---|---|---|---|---|---|
| CALL | F | ? | 1 | CS: value | PC value | |
| GOTO | F | ? | 2 | CS: value | PC value |
The target address is formed by the immediate6 value (for CS:) and another word after the instruction (for PC)
Interrupts
| Instruction | Opcode0 | Operand A | Opcode1 | 6-bit Immediate |
|---|---|---|---|---|
| INT OFF | F | 0 | 5 | 00 |
| INT IRQ | F | 0 | 5 | 01 |
| INT FIQ | F | 0 | 5 | 02 |
| INT IRQ,FIQ | F | 0 | 5 | 03 |
| FIR_MOV ON | F | 0 | 5 | 04 |
| FIR_MOV OFF | F | 0 | 5 | 05 |
| IRQ OFF | F | 0 | 5 | 08 |
| IRQ ON | F | 0 | 5 | 09 |
| FIQ OFF | F | 0 | 5 | 0C |
| FIQ ON | F | 0 | 5 | 0E |
| NOP | F | 0 | 5 | 25 |
probably other instructions (FRACTION, …) fit in here
Jump instructions
Jump instructions are identified by Operand A = 7 (makes sense, because they change the PC which is register 7)
| Instruction | Opcode0 | Operand A | Opcode1 | 6-bit Immediate |
|---|---|---|---|---|
| JCC, JB, JNAE | 0 | 7 | Direction | Jump offset |
| JCS, JNB, JAE | 1 | 7 | Direction | Jump offset |
| JSC, JGE, JNL | 2 | 7 | Direction | Jump offset |
| JSS, JNGE, JL | 3 | 7 | Direction | Jump offset |
| JNE, JNZ | 4 | 7 | Direction | Jump offset |
| JE, JZ | 5 | 7 | Direction | Jump offset |
| JPL | 6 | 7 | Direction | Jump offset |
| JMI | 7 | 7 | Direction | Jump offset |
| JBE, JNA | 8 | 7 | Direction | Jump offset |
| JNBE, JA | 9 | 7 | Direction | Jump offset |
| JLE, JNG | A | 7 | Direction | Jump offset |
| JNLE, JG | B | 7 | Direction | Jump offset |
| JVC | C | 7 | Direction | Jump offset |
| JVS | D | 7 | Direction | Jump offset |
| JMP | E | 7 | Direction | Jump offset |
| F | 7 | Reserved for special instructions | ||
Opcode1 indicates the jump direction, and can be 0 (jump back) or 1 (jump forward)
ALU instructions
| Instruction | Opcode0 | Operand A | Opcode1 | OPN | Operand B |
|---|---|---|---|---|---|
| ADD | 0 | Op. A | Addr Mode | Param | Op. B |
| ADC | 1 | Op. A | Addr Mode | Param | Op. B |
| SUB | 2 | Op. A | Addr Mode | Param | Op. B |
| SBC | 3 | Op. A | Addr Mode | Param | Op. B |
| CMP | 4 | Op. A | Addr Mode | Param | Op. B |
| NEG | 6 | Op. A | Addr Mode | Param | Op. B |
| XOR | 8 | Op. A | Addr Mode | Param | Op. B |
| LD | 9 | Op. A | Addr Mode | Param | Op. B |
| POP | 9 | First reg - 1 | 2 | Register count | Stack pointer reg |
| OR | A | Op. A | Addr Mode | Param | Op. B |
| AND | B | Op. A | Addr Mode | Param | Op. B |
| TEST | C | Op. A | Addr Mode | Param | Op. B |
| ST | D | Op. A | Addr Mode | Param | Op. B |
| PUSH | D | Op. A | 2 | Param | Op. B |
| F | Reserved for special instructions | ||||
For these instructions, Opcode1 defines the addressing mode:
- 0: [BP+Imm6]
- 1: #Imm6
- 2: special functions: push, pop, reti and retf
- 3: [Rs]
- 4: addressing depends on opN
- 5: Rs LSL/LSR OpN
- 6: Rs ROL/ROR OpN
- 7: [Imm6]
In a POP instruction:
- OperandA+1 is the first popped register (it is not possible to push R0/SP)
- OperandN is the number of registers to push
- OperandB is the register to use as a stack pointer
RETF is a special case of POP with opA=5, opN=2, opB=0 (restores R6 and R7)
RETI is a special case of POP with opA=5, opN=3, opB=0 (restores R6, R7, and an extra special register containing interrupt flags)
In a PUSH instruction:
- OperandA+1 is the last pushed register
- OperandN is the number of registers to push
- OperandB is the register to use as a stack pointer
When opcode1 is 3, operandN defines incrementation and use of DS:
- 0: [Rs]
- 1: [Rs–]
- 2: [Rs++]
- 3: [++Rs]
- 4: DS:[Rs]
- 5: DS:[Rs–]
- 6: DS:[Rs++]
- 7: DS:[++Rs]
When opcode1 is 4, operandN defines more addressing modes:
- 0: Rs
- 1: 16-bit immediate value
- 2: Load from memory address
- 3: Store to memory address
- 4: Rs ASR 1
- 5: Rs ASR 2
- 6: Rs ASR 3
- 7: Rs ASR 4
When opcode1 is 5 or 6, operandN MSB defines the shift direction, and the 2 other bits define the amount of shifting (1 to 4 bits)
