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memory_map [2021/08/30 20:49] – [IO registers] pulkomandy | memory_map [2021/09/23 22:48] – [UART] pulkomandy | ||
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Line 6: | Line 6: | ||
| 0x003000 | | 0x003000 | ||
| 0x003D00 | | 0x003D00 | ||
- | | 0x003e00 | + | | 0x003E00 |
External memory starts at 0x4000. It can be mapped to the internal ROM and the two possible chips in the cartridges. | External memory starts at 0x4000. It can be mapped to the internal ROM and the two possible chips in the cartridges. | ||
Line 44: | Line 44: | ||
If the attribute bit is 1, there is no inversion, and the data bit is output as is. | If the attribute bit is 1, there is no inversion, and the data bit is output as is. | ||
- | |||
- | ===== IO special functions and usage ===== | ||
- | |||
- | FIXME this does not match the info from the V.Smile motion schematics (see [[IO]] page). Where does this info come from (except from bmx spreadsheet) and which is correct? | ||
- | |||
- | * IOA15: act | ||
- | * IOA14-0: 15 bit RGB | ||
- | * IOA15: SCK | ||
- | * IOA14: SDA | ||
- | * IOA13: SWS | ||
- | * IOA12: CKV | ||
- | * IOA11: FM | ||
- | * IOA10: FP | ||
- | * IOA9: LP | ||
- | * IOA8: CP | ||
- | * IOA7-0: D7-0 | ||
- | * IOC15: SPI clock | ||
- | * IOC14: RX | ||
- | * IOC13: TX | ||
- | * IOC12: SPI SSB | ||
- | * IOC11: TFT Clock | ||
- | * IOC10: timebase 1 | ||
- | * IOC9: TAPWM | ||
- | * IOC8: VSYNC | ||
- | * IOC7: HSYNC | ||
- | * IOC1: timebase 2 / external clock 1 input | ||
- | * IOC0: TBPWM / external clock 2 input | ||
Line 90: | Line 63: | ||
| 3D1C | Scanline counter | | 3D1C | Scanline counter | ||
- | Timebase values: | + | Timebase |
- | + | | |
- | - 00: TMB2 = 128Hz, TMB1 = 8Hz | + | * 00 - 128 Hz |
- | - 01: TMB2 = 256Hz, TMB1 = 16Hz | + | * 01 - 256 Hz |
- | - 10: TMB2 = 512Hz, | + | * 10 - 512 Hz |
- | - 11: TMB2 = 1024Hz, TMB1 = 64Hz | + | * 11 - 1024 Hz |
+ | | ||
+ | * 00 - 8 Hz | ||
+ | * 01 - 16 Hz | ||
+ | * 10 - 32 Hz | ||
+ | * 11 - 64 Hz | ||
===== Timer A ===== | ===== Timer A ===== | ||
Line 155: | Line 133: | ||
| 3D2D | Pseudo Random2 | | 3D2D | Pseudo Random2 | ||
| 3D2E | FIQ Sel | | 3D2E | FIQ Sel | ||
- | | 3D2F | DS register | + | | 3D2F | DS register |
===== System control ===== | ===== System control ===== | ||
Line 202: | Line 180: | ||
| FFFD | IRQ5 |External interrupts | | FFFD | IRQ5 |External interrupts | ||
| FFFE | IRQ6 |1024, 2048 or 4096Hz ticker | | | FFFE | IRQ6 |1024, 2048 or 4096Hz ticker | | ||
- | | FFFF | IRQ7 |4Hz ticker, | + | | FFFF | IRQ7 |4Hz ticker, |
As the vector addresses are only 16-bit, they can only point to the first segment (0x0000 - 0xFFFF). | As the vector addresses are only 16-bit, they can only point to the first segment (0x0000 - 0xFFFF). | ||
===== External bus configuration ===== | ===== External bus configuration ===== | ||
- | * Bits 11-8: Ram decode control | + | * Bits 11-8: External RAM decode control |
- | * Bits 7-6: Address | + | * 0xxx - No mapping |
- | * Bits 5-3: Bus arbitration control | + | * 1000 - Map '' |
+ | * 1001 - Map '' | ||
+ | * 1010 - Map '' | ||
+ | * 1011 - Map '' | ||
+ | * 1100 - Map '' | ||
+ | * 1101 - Map '' | ||
+ | * 1110 - Map '' | ||
+ | * 1111 - Map '' | ||
+ | * Bits 7-6: ROM address | ||
+ | * 00 - Map entire range to ROMCSB | ||
+ | * 01 - Map '' | ||
+ | * 1x - Map '' | ||
+ | * Bits 5-3: Bus arbitration | ||
+ | * 101 - 1. Audio, 2. PPU, 3. CPU | ||
+ | * 111 - 1. PPU, 2. Audio, 3. CPU | ||
* Bits 2-1: Number of wait states | * Bits 2-1: Number of wait states | ||
* Bit 0: CKOEN | * Bit 0: CKOEN | ||
+ | |||
+ | External RAM mapping overrides any ROM mapping. | ||
==== ADC ==== | ==== ADC ==== | ||
Line 285: | Line 279: | ||
* 115200: FF F1 | * 115200: FF F1 | ||
+ | Before using the UART, the corresponding PINs need to be configured properly. IOC13 and IOC14 must be set to " | ||
+ | The example below also forces CTS A (IOC8) low, allowing the first controller port to transmit data. Normally this would only be done after receiving an RTS from said controller. | ||
+ | |||
+ | // Enable controller CTS | ||
+ | *PORTC_DIR = 0x89c0; | ||
+ | *PORTC_ATTR = 0x89c0; | ||
+ | *PORTC_DATA = 0xf77f; | ||
+ | |||
+ | // Enable Uart RX (controller input) | ||
+ | *UART_BAUDRATE_LOW = 0xA0; | ||
+ | *UART_BAUDRATE_HIGH = 0xFE; | ||
+ | *UART_CONTROL = 0xc3; | ||
+ | *UART_STATUS = 3; | ||
+ | |||
+ | *PORTC_SPECIAL |= 0x6000; // UART Tx and Rx in " | ||
+ | *PORTC_ATTR |= 0x6000; | ||
+ | *PORTC_DIR |= 0x4000; | ||
+ | |||
+ | Reading from the UART then is quite simple: | ||
+ | |||
+ | * Wait until the status register indicates Rx ready (bit 0) | ||
+ | * When Rx is ready, read the Rx data register to get the byte | ||
+ | |||
+ | For transmitting, | ||
====== SPI ====== | ====== SPI ====== | ||