Differences
This shows you the differences between two versions of the page.
Both sides previous revisionPrevious revisionNext revision | Previous revisionNext revisionBoth sides next revision | ||
pinouts [2021/03/11 16:44] – [Battery backup cartridge] pulkomandy | pinouts [2021/08/29 21:37] – [V.Smile cartridges] pulkomandy | ||
---|---|---|---|
Line 17: | Line 17: | ||
^Back |VDD|RAM CSB|Sense|ROM CSB2|D2|D1|D0|D7 |D10|D9 |D8 |D14|A16|A2^x |A4|A6|A17|A8|A10|A12|A14|A19|A21|ROM CSB1 | | ^Back |VDD|RAM CSB|Sense|ROM CSB2|D2|D1|D0|D7 |D10|D9 |D8 |D14|A16|A2^x |A4|A6|A17|A8|A10|A12|A14|A19|A21|ROM CSB1 | | ||
- | **Note: the " | + | **Note: the " |
* Sense is connected to VDD to indicate that a cart is inserted. It is connected to the RESET pin, so inserting a cartridge will power the console off. | * Sense is connected to VDD to indicate that a cart is inserted. It is connected to the RESET pin, so inserting a cartridge will power the console off. | ||
- | * Card detect is connected to VDD to indicate that a cart with ROM is inserted (?) | + | * Card detect is connected to VDD to indicate that a cart with ROM is inserted (?) maybe it allows booting from cartridge instead of internal ROM (tbc) |
- | * ROM CSB1, ROM CSB2 and RAM CSB allow to select which bank of the cartridge is accessed. Typically cartridges use only ROM CSB1. | + | * ROM CSB1, ROM CSB2 and RAM CSB allow to select which bank of the cartridge is accessed. Typically cartridges use only ROM CSB1, but larger cartridges (example: alphabet adventure) need two ROM banks. ROM_CSB2 may also be used for battery-backed SRAM. The two pins are controlled independently as GPIO from the CPU, so all 4 combinations are possible. However, 11 will be used when the internal ROM is accessed, so it's better to have the cartridge idle in that case. |
To be confirmed: | To be confirmed: | ||
- | * Which carts use ROM_CSB2? Is it for games larger than 8MB to use two flash chips? | + | * What is RAM_CSB? It is not connected on the only cart known to use SRAM. The name of the pin comes from schematics of the console but it just shows that it is connected to the SPG200C without any other info. SPCE1600 datasheet shows it would be usable for external RAM, where in the address |
- | * What is the max capacity? Since we have 3 bits (RAM_CSB, ROM_CSB1 and ROM_CSB2), can we fully control them individually and address | + | |
==== Battery backup cartridge ==== | ==== Battery backup cartridge ==== | ||
Line 37: | Line 35: | ||
{{: | {{: | ||
+ | The blob is flash (as usual) and the chip on the right is RAM: BSI - [[https:// | ||
+ | |||
+ | The pin labelled RAM_CSB in the pinout above is in fact not used by this cartridge (but ROM_CSB2 is) | ||
+ | |||
+ | ==== Dual ROM cartridges ==== | ||
+ | |||
+ | At least the following games have two blobs on ROM_CSB1 and ROM_CSB2: | ||
+ | |||
+ | * The little mermaid | ||
+ | * Smart keyboard | ||
+ | * Alphabet adventure | ||
===== Nitro Vision / Genius TV progress cartridges ===== | ===== Nitro Vision / Genius TV progress cartridges ===== | ||
Line 66: | Line 75: | ||
- RTS (from controller) | - RTS (from controller) | ||
+ | {{ : | ||
+ | {{ :: | ||
===== Flow control ===== | ===== Flow control ===== | ||
Line 157: | Line 168: | ||
* Down: 70 8F | * Down: 70 8F | ||
* Up: 70 87 | * Up: 70 87 | ||
+ | |||
+ | Boot sequence: | ||
+ | |||
+ | * Keyboard sends 52 52 52 | ||
+ | * Console sends 0x02 0x02 0xE6 0xD6 0x60 | ||
+ | * Keyboard sends language code | ||
+ | * Console: 0x70 | ||
+ | * Keyboard: 0xBA | ||
+ | |||
+ | The language codes: | ||
+ | |||
+ | * 0x40: US | ||
+ | * 0x41: UK | ||
+ | * 0x42: French | ||
+ | * 0x44: German | ||
===== Commands from the console ===== | ===== Commands from the console ===== | ||