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ppu [2021/09/05 17:03]
– [Colors and palettes] simer
ppu [2021/09/05 18:10] (current)
– [Layer 1 and 2 registers] simer
Line 78: Line 78:
   * Bit 2: Mirror the tiles horizontally   * Bit 2: Mirror the tiles horizontally
   * Bit 3: Mirror the tiles vertically   * Bit 3: Mirror the tiles vertically
-  * Bits 4 and 5: Width of tiles+  * Bits 4-5: Width of tiles
     * 00 - 8 pixels     * 00 - 8 pixels
     * 01 - 16 pixels     * 01 - 16 pixels
     * 10 - 32 pixels     * 10 - 32 pixels
     * 11 - 64 pixels     * 11 - 64 pixels
-  * Bits 6 and 7: Height of tiles+  * Bits 6-7: Height of tiles
       * Same format as width register       * Same format as width register
-  * Bits 8 to 11: Palette bank to use +  * Bits 8-11: Palette bank to use 
-  * Bits 12 and 13: Layer depth (wether it is under or over sprites and the other layer)+  * Bits 12-13: Layer depth (wether it is under or over sprites and the other layer)
       * 00 - bottom layer       * 00 - bottom layer
       * 01 - second-bottom layer       * 01 - second-bottom layer
       * 10 - second-top layer       * 10 - second-top layer
       * 11 - top layer       * 11 - top layer
-  * Bits 14 and 15: unused (in later PPU generations it sets the layer size)+  * Bits 14-15: unused (in later PPU generations it sets the layer size)
  
 The control register can do the following: The control register can do the following:
Line 106: Line 106:
  
 When the attribute map mode is used, each word stores attributes for one tile in each byte in the following format: When the attribute map mode is used, each word stores attributes for one tile in each byte in the following format:
-  * Bits 0 to 3: Palette bank to use+  * Bits 0-3: Palette bank to use
   * Bit 4: Mirror the tiles horizontally   * Bit 4: Mirror the tiles horizontally
   * Bit 5: Mirror the tiles vertically   * Bit 5: Mirror the tiles vertically
ppu.txt · Last modified: 2021/09/05 18:10 by simer
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