Differences
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| Both sides previous revisionPrevious revisionNext revision | Previous revision | ||
| instruction_encoding [2024/05/12 09:44] – [Summary] pulkomandy | instruction_encoding [2024/07/01 13:29] (current) – [Multiplication] simer | ||
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| Line 44: | Line 44: | ||
| Note: Operand A and Operand B cannot be 0, 6 or 7 (it is not possible to multiply SP, SR or PC with something). | Note: Operand A and Operand B cannot be 0, 6 or 7 (it is not possible to multiply SP, SR or PC with something). | ||
| They also can not be 3 or 4 in MAC (MR is used for intermediate results). If the size of the MAC | They also can not be 3 or 4 in MAC (MR is used for intermediate results). If the size of the MAC | ||
| - | operation is exactly 16, it will be stored | + | operation is exactly 16, it will be encoded |
| ==== CALL and GOTO ==== | ==== CALL and GOTO ==== | ||
| Line 137: | Line 137: | ||
| ^%% D: | ^%% D: | ||
| ^%% Rs %%| ALU op| Op. A | 4 | 0 | Rs | | ^%% Rs %%| ALU op| Op. A | 4 | 0 | Rs | | ||
| - | ^%% # | + | ^%% # |
| - | ^%% From [Addr16] %%| ALU op| Op. A | 4 | 2 | Unused | + | ^%% From [Addr16] %%| ALU op| Op. A | 4 | 2 | Rs* | |16-bit address in next word, Rs is first operand| |
| - | ^%% To [Addr16] | + | ^%% To [Addr16] |
| ^%% Rs ASR shift %%| ALU op| Op. A | 4 | 4 + (shift - 1) | Rs | | ^%% Rs ASR shift %%| ALU op| Op. A | 4 | 4 + (shift - 1) | Rs | | ||
| ^%% Rs LSL shift %%| ALU op| Op. A | 5 | shift - 1 | Rs | | ^%% Rs LSL shift %%| ALU op| Op. A | 5 | shift - 1 | Rs | | ||
