Instruction set documentation archived from “unSP Programmer's Guide” PDF from the unSP IDE installation - local copy. A good overview can also be found in this document.

The V-Smile processor is a Sunplus µ'nSP implementing version 1.1 of the ISA (source: this is how the SPG200 projects in µ'nSP IDE are configured).

R3 and R4 can be used to form a 32-bit register pair for some instructions, this pair is noted MR. R3 stores the lower half and R4 stores the upper half.

There is also a 4-bit shift buffer (SB) register used by the shift and rotate addressing modes. There are separate SB registers for normal, FIQ and interrupt mode, which gets automatically switched.

The BP register has a special addressing mode with a 6-bit immediate offset. It is usually (for example by unsp IDE C compiler) used as a frame pointer, to access a function local variables efficiently. But it can also be used as a normal register if needed.

SP is generally used as a stack pointer but can be used for other things occasionally. When using the PUSH and POP instructions, the stack grows downwards (PUSH decrements SP) and the stack pointer points to the first empty space below the stack.

As a result, the typical organization of the stack in VTech code is:

The SP can move when calling other functions, interrupts, … or when saving registers inside the function code. But BP doesn't move and can be used to access both local variables and function parameters.

The parameters are usually removed by the caller (by incrementing SP). It would also be possible to use a POP including SR and PC to return from the function while clearing parameters, but this requires loading them into registers, which is not always desirable since registers are rather used for return values.

The status register contains various status flags, as well as the current code segment (CS) and data segment (DS) base addresses.

The memory map of the µ'nSP is split into 64K sized pages. The entire 4M address space of the CPU is divided into 64 pages (0x00-0x3F). The current page can be selected via the segment registers, CS (for instruction fetch) and DS (for data operations).

When code execution reaches the end of the current page, the CS register is auto-incremented by the hardware.

The interrupt vector table is at the end of the first memory page. It contains addresses of the handlers for each interrupt, including the software interrupt (BREAK instruction) and CPU reset. Since the addresses are only 16bit, all handlers must be in the first memory page.

See http://vtech.pulkomandy.tk/doku.php?id=memory_map&s%5B%5D=irq#interrupts for details about the interruptions usage.

These tables detail the instruction both in the format used by the official µ'nSP toolchain as well as the mnemonic form used by the free for non-commercial use vasm.

NOTE: Unless otherwise specified, instructions that operate on memory ignore DS and only operate on page 0 (0x0000-0xFFFF). Instruction varients that allow a “D:” prefix generate a full 22-bit address via (DS << 16 | addr)

The stack grows downwards (towards lower addresses). Push does post-decrement so SP points to the unused entry at the top of the stack.

Values before pushing:

SP = FFFE

PUSH BP, [SP]

Values after pushing:

SP = FFFD

All these operations have similar syntax and support the same addressing modes

For all ALU operations, the following addressing modes are available:

It is possible to combine indirect with data segment and increments and decrements in the same instruction. The data segment will then be automatically updated in case the increment or decrement wraps.

The shift operations use the shift buffer (see “shift operations” section below). In particular the ROR and ROL operations do a 20-bit rotation resulting in bits from the shift buffer moving into the destination register.

Given a starting register like this:

And the SB bits:

The result of the shift operations are (for a shift by 3 bits):

Arithmetic shift right (signed divide by two)

Logical shift left (multiply by two)

Logical shift right (unsigned divide by two)

Rotate left through shift buffer

Rotate right through shift buffer

Multiplication result is stored in R3 and R4 (the register pair is called MR)

Multiply-accumulate operations do the computation with 32-bit precision with the result is stored in MR. The Rd and Rs pointers will automatically be incremented by N. The values of the array pointed to by the Rd array will each be moved one index forward when the FIR_MOV setting is enabled, see the FIR_MOV section for details.

FIR_MOV ON

FIR_MOV OFF

Affects the FIR setting used by the MULS instructions.

When enabled, MULS instructions will modify the array pointed to by the Rd register after finishing the calculation by moving each value one index forward with the last value discarded and the first value left in place. This can be used for automatically advancing the time step when implementing FIR filters, with the Rd array storing the input signal and the Rs array storing the weights.

Syntax:

JMP label

The target address is stored as a 6 bit displacement and a separate bit indicating forward or backward jump. So this can only jump back and forward 63 addresses.

xasm supports the syntax SJMP for “smart jump” that will automatically be converted to a jump + GOTO if the address is outside the reachable range for a normal jump.

CALL label

• PC and SR are pushed to the stack
• PC and the code segment part of SR are loaded with the 22-bit parameter address

Because SR is pushed automatically, flags are always saved accross a CALL/RETF

Like a call, but does not save PC and SR on the stack. In ISA 1.0, GOTO does not set the CS: so it is not possible to jump outside the current segment. In ISA 1.1 and above this problem is fixed.

Return from function. Pops PC and SR from the stack.

Return from interrupt. In addition to what RETF does, also restores the interrupt flag.

Jumps to the BREAK software IRQ handler.