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| Both sides previous revisionPrevious revisionNext revision | Previous revision | ||
| memory_map [2021/09/05 16:12] – [Misc. peripherals] simer | memory_map [2024/07/01 11:27] (current) – ↷ Links adapted because of a move operation admin | ||
|---|---|---|---|
| Line 4: | Line 4: | ||
| | 0x000000 | | 0x000000 | ||
| | 0x002800 | | 0x002800 | ||
| - | | 0x003000 | + | | 0x003000 |
| | 0x003D00 | | 0x003D00 | ||
| | 0x003E00 | | 0x003E00 | ||
| Line 31: | Line 31: | ||
| The direction register is 0 for input pins, 1 for output pins. | The direction register is 0 for input pins, 1 for output pins. | ||
| + | ===== Global configuration register ===== | ||
| + | |||
| + | * Bit 0: IOA special functions select | ||
| + | * Bit 1: IOB special functions select | ||
| + | |||
| + | These two bits allow to select one of two special functions for the IOA and IOB registers. Then each pin in that IO register can be switched between normal GPIO and special function using the MASK register. | ||
| + | |||
| + | For IOA, special = 0 selects the TFT display interface, special = 1 selects the STN LCD interface and I2S audio output. | ||
| + | |||
| + | For IOB, only special = 0 is documented and it selects the CSB0, CSB1, CSB2 chip select pins for external memory (further configured by port 3D23) | ||
| + | |||
| + | * Bit 2: IOA Wakeup enable | ||
| + | * Bit 3: IOB Wakeup enable | ||
| + | * Bit 4: IOC Wakeup enable | ||
| + | |||
| + | These bits enable system wakeup from sleep mode from activity on the corresponding IO ports. A typical setup on the V.Smile is to enable wakeup on port B to detect when the ON button is pressed. | ||
| ===== Input pins configuration ===== | ===== Input pins configuration ===== | ||
| Line 44: | Line 60: | ||
| If the attribute bit is 1, there is no inversion, and the data bit is output as is. | If the attribute bit is 1, there is no inversion, and the data bit is output as is. | ||
| - | |||
| - | ===== IO special functions and usage ===== | ||
| - | |||
| - | FIXME this does not match the info from the V.Smile motion schematics (see [[IO]] page). Where does this info come from (except from bmx spreadsheet) and which is correct? | ||
| - | |||
| - | * IOA15: act | ||
| - | * IOA14-0: 15 bit RGB | ||
| - | * IOA15: SCK | ||
| - | * IOA14: SDA | ||
| - | * IOA13: SWS | ||
| - | * IOA12: CKV | ||
| - | * IOA11: FM | ||
| - | * IOA10: FP | ||
| - | * IOA9: LP | ||
| - | * IOA8: CP | ||
| - | * IOA7-0: D7-0 | ||
| - | * IOC15: SPI clock | ||
| - | * IOC14: RX | ||
| - | * IOC13: TX | ||
| - | * IOC12: SPI SSB | ||
| - | * IOC11: TFT Clock | ||
| - | * IOC10: timebase 1 | ||
| - | * IOC9: TAPWM | ||
| - | * IOC8: VSYNC | ||
| - | * IOC7: HSYNC | ||
| - | * IOC1: timebase 2 / external clock 1 input | ||
| - | * IOC0: TBPWM / external clock 2 input | ||
| Line 225: | Line 214: | ||
| * 00 - Map entire range to ROMCSB | * 00 - Map entire range to ROMCSB | ||
| * 01 - Map '' | * 01 - Map '' | ||
| - | * 1x - Map '' | + | * 1x - Map '' |
| * Bits 5-3: Bus arbitration priority control | * Bits 5-3: Bus arbitration priority control | ||
| * 101 - 1. Audio, 2. PPU, 3. CPU | * 101 - 1. Audio, 2. PPU, 3. CPU | ||
| Line 233: | Line 222: | ||
| External RAM mapping overrides any ROM mapping. | External RAM mapping overrides any ROM mapping. | ||
| + | |||
| + | On the V.Smile, both ROMCSB and CSB1 allow to access the cartridge ROM. This means bit 6 is not very useful. | ||
| + | |||
| + | CSB2 is the cartridge RAM, and CSB3 is the system ROM. They are both enabled at the same time by using bit 7. | ||
| ==== ADC ==== | ==== ADC ==== | ||
| Line 306: | Line 299: | ||
| * 115200: FF F1 | * 115200: FF F1 | ||
| + | Before using the UART, the corresponding PINs need to be configured properly. IOC13 and IOC14 must be set to " | ||
| + | The example below also forces CTS A (IOC8) low, allowing the first controller port to transmit data. Normally this would only be done after receiving an RTS from said controller. | ||
| + | |||
| + | // Enable controller CTS | ||
| + | *PORTC_DIR = 0x89c0; | ||
| + | *PORTC_ATTR = 0x89c0; | ||
| + | *PORTC_DATA = 0xf77f; | ||
| + | |||
| + | // Enable Uart RX (controller input) | ||
| + | *UART_BAUDRATE_LOW = 0xA0; | ||
| + | *UART_BAUDRATE_HIGH = 0xFE; | ||
| + | *UART_CONTROL = 0xc3; | ||
| + | *UART_STATUS = 3; | ||
| + | |||
| + | *PORTC_SPECIAL |= 0x6000; // UART Tx and Rx in " | ||
| + | *PORTC_ATTR |= 0x6000; | ||
| + | *PORTC_DIR |= 0x4000; | ||
| + | |||
| + | Reading from the UART then is quite simple: | ||
| + | |||
| + | * Wait until the status register indicates Rx ready (bit 0) | ||
| + | * When Rx is ready, read the Rx data register to get the byte | ||
| + | |||
| + | For transmitting, | ||
| ====== SPI ====== | ====== SPI ====== | ||
