Differences
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| Both sides previous revisionPrevious revisionNext revision | Previous revision | ||
| memory_map [2021/09/23 20:48] – [UART] pulkomandy | memory_map [2024/07/01 11:27] (current) – ↷ Links adapted because of a move operation admin | ||
|---|---|---|---|
| Line 4: | Line 4: | ||
| | 0x000000 | | 0x000000 | ||
| | 0x002800 | | 0x002800 | ||
| - | | 0x003000 | + | | 0x003000 |
| | 0x003D00 | | 0x003D00 | ||
| | 0x003E00 | | 0x003E00 | ||
| Line 31: | Line 31: | ||
| The direction register is 0 for input pins, 1 for output pins. | The direction register is 0 for input pins, 1 for output pins. | ||
| + | ===== Global configuration register ===== | ||
| + | |||
| + | * Bit 0: IOA special functions select | ||
| + | * Bit 1: IOB special functions select | ||
| + | |||
| + | These two bits allow to select one of two special functions for the IOA and IOB registers. Then each pin in that IO register can be switched between normal GPIO and special function using the MASK register. | ||
| + | |||
| + | For IOA, special = 0 selects the TFT display interface, special = 1 selects the STN LCD interface and I2S audio output. | ||
| + | |||
| + | For IOB, only special = 0 is documented and it selects the CSB0, CSB1, CSB2 chip select pins for external memory (further configured by port 3D23) | ||
| + | |||
| + | * Bit 2: IOA Wakeup enable | ||
| + | * Bit 3: IOB Wakeup enable | ||
| + | * Bit 4: IOC Wakeup enable | ||
| + | |||
| + | These bits enable system wakeup from sleep mode from activity on the corresponding IO ports. A typical setup on the V.Smile is to enable wakeup on port B to detect when the ON button is pressed. | ||
| ===== Input pins configuration ===== | ===== Input pins configuration ===== | ||
| Line 198: | Line 214: | ||
| * 00 - Map entire range to ROMCSB | * 00 - Map entire range to ROMCSB | ||
| * 01 - Map '' | * 01 - Map '' | ||
| - | * 1x - Map '' | + | * 1x - Map '' |
| * Bits 5-3: Bus arbitration priority control | * Bits 5-3: Bus arbitration priority control | ||
| * 101 - 1. Audio, 2. PPU, 3. CPU | * 101 - 1. Audio, 2. PPU, 3. CPU | ||
| Line 206: | Line 222: | ||
| External RAM mapping overrides any ROM mapping. | External RAM mapping overrides any ROM mapping. | ||
| + | |||
| + | On the V.Smile, both ROMCSB and CSB1 allow to access the cartridge ROM. This means bit 6 is not very useful. | ||
| + | |||
| + | CSB2 is the cartridge RAM, and CSB3 is the system ROM. They are both enabled at the same time by using bit 7. | ||
| ==== ADC ==== | ==== ADC ==== | ||
