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Table of Contents
| Start | End | Description |
|---|---|---|
| 0x000000 | 0x0027FF | RAM |
| 0x002800 | 0x002FFF | PPU |
| 0x003000 | 0x0037FF | Sound |
| 0x003D00 | 0x003DFF | IO |
| 0x003e00 | 0x003E03 | DMA |
External memory starts at 0x4000. It can be mapped to the internal ROM and the two possible chips in the cartridges.
Document how to manipulate the banking (using GPIOs?)
IO registers
| Address | Contents |
|---|---|
| 3D00 | IO configuration |
| 3D01-3D05 | IOA registers |
| 3D06-3D0A | IOB registers |
| 3D0B-3D0F | IOC registers |
| 1/6/B | IOx data |
| 2/7/C | IOx buffer |
| 3/8/D | IOx direction |
| 4/9/E | IOx attributes |
| 5/A/F | IOx mask |
IO special functions and usage:
- IOA15: act
- IOA14-0: 15 bit RGB
- IOA15: SCK
- IOA14: SDA
- IOA13: SWS
- IOA12: CKV
- IOA11: FM
- IOA10: FP
- IOA9: LP
- IOA8: CP
- IOA7-0: D7-0
- IOC15: SPI clock
- IOC14: RX
- IOC13: TX
- IOC12: SPI SSB
- IOC11: TFT Clock
- IOC10: timebase 1
- IOC9: TAPWM
- IOC8: VSYNC
- IOC7: HSYNC
- IOC1: timebase 2 / external clock 1 input
- IOC0: TBPWM / external clock 2 input
Cartridge banks selection
These IO pins allow to map either the internal ROM or the two different cartridge banks into memory.
- IOB2: CSB3
- IOB1: CSB2
- IOB0: CSB0
Timers
3D10 Timebase setup TMB2 freq TMB1 freq
00 TMB2 128Hz TMB1 8Hz 01 256Hz 16Hz 10 512Hz 32Hz 11 1024Hz 64Hz
3D11 Timebase clear 3D12 TimerA Data 3D13 TimerA Control output_pulse_ctrl source B select bits source A select bits 3D14 TimerA ON on/off 3D15 TimerA IRQCLR clear 3D16 TimerA DATA 3D17 TimerB Control output_pulse_ctrl source C select bits 3D18 TimerB ON on/off 3D19 TimerB IRQCLR clear 3D1C Line counter
Misc. peripherals
3D20 System Control Watchdog sleep LVR OE LV en #2V out LVD volt select #32K clk #Vid DAC #Aud DAC 3D21 INT Ctrl ADC Ext2 TimerA TimerB Ext1 UART Key Chg 4096Hz 2048Hz 1024Hz 4Hz TMB2 TMB1
interrupt vector FFFB FFFD FFFA FFFA FFFD FFFB FFFF FFFE FFFE FFFE FFFF FFFF FFFF
3D22 INT clear ADC Ext2 TimerA TimerB Ext1 UART Key Chg 4096Hz 2048Hz 1024Hz 4Hz TMB2 TMB1
read status SPI ADC Ext2 TimerA TimerB Ext1 UART Key Chg 4096Hz 2048Hz 1024Hz 4Hz TMB2 TMB1
3D23 Ext Memory Ctrl Ram Decode Control Addr Decode Ctrl Bus Arbitrer Control Wait State Number CKOEN 3D24 Watchdog clear 5 5 A A 3D25 ADC Control int status req auto req int_en VRT_En CH_Sel CLK_Sel CSB ADE 3D27 ADC DATA rdy adc data 3D28 Sleep Mode A A 5 5 3D29 Wakeup Source key 4KHz 2KHz 1KHz 4Hz 2Hz tmb2 tmb1 3D2A Wakeup Time num of 32KHz clock cycles 3D2B TV System read only NTSC/Pal 3D2C Pseudo Random1 f(x) = x^15+x^14+1, default seed = 001_0100_0001_1000, write to set new seed (15bits) 3D2D Pseudo Random2 same, default seed = 001_0110_0101_1000 3D2E FIQ Sel fiq_sel
000 PPU 010 TimerA 100 UART(SPI) 110 ADC 001 SPU 011 TimerB 101 External 111 None
3D2F DataSegment Access DS
UART
3D30 UART Control TxEn RxEn Mode MulPro 9th bit TxIntEn RxIntEn 3D31 UART Status rxbf txbusy bit9 overrun frame parity txrdy rxrdy 3D32 UART Reset reset 3D33 UART Baud Scalar Low 1200: FA92, 2400: FD41, 4800: FEA0, 9600: FF50, 19200: FFA8 low byte 3D34 UART Baud Scalar Hi 57600: FFE2, 115200: FFF1 high byte 3D35 UART TxBUF uart_txbuf 3D36 UART RxBUF uart_rxbuf
SPI
3D40 SPI Control busy txempty rxfull SPH SPO SPIEN LPM TxIntEn RxIntEn 3D41 SPI DATA data (read receive, write transmit) 3D42 SPI Div serial clock rate clock pre-scale divisor
General DMA
3E00 DMA Src Addr Low source address [15:0] 3E01 DMA Src Addr High source address [21:16] 3E02 DMA Number dma number [13:0] (write number of words here to start the transfer) 3E03 DMA Target Address target address [13:0]
