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memory_map [2021/08/26 21:31] – [Cartridge banks selection] pulkomandymemory_map [2023/04/16 10:15] (current) – [External bus configuration] pulkomandy
Line 6: Line 6:
 | 0x003000  | 0x0037FF  | [[Sound]]   | | 0x003000  | 0x0037FF  | [[Sound]]   |
 | 0x003D00  | 0x003DFF  | [[IO]]      | | 0x003D00  | 0x003DFF  | [[IO]]      |
-0x003e00  | 0x003E03  | [[memory_map#General DMA|DMA]]     |+0x003E00  | 0x003E03  | [[memory_map#General DMA|DMA]]     |
  
 External memory starts at 0x4000. It can be mapped to the internal ROM and the two possible chips in the cartridges. External memory starts at 0x4000. It can be mapped to the internal ROM and the two possible chips in the cartridges.
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 | 5/A/F     | IOx mask         | | 5/A/F     | IOx mask         |
  
-IO special functions and usage:+Each IO port is configured by 4 registers.
  
-FIXME this does not match the info from the V.Smile motion schematics (see [[IO]] page). Where does this info come from (except from bmx spreadsheet) and which is correct?+The direction register is 0 for input pins, 1 for output pins.
  
-  * IOA15: act +===== Global configuration register ===== 
-  * IOA14-0: 15 bit RGB + 
-  * IOA15SCK +  * Bit 0: IOA special functions select 
-  * IOA14: SDA +  * Bit 1IOB special functions select 
-  * IOA13: SWS + 
-  * IOA12: CKV +These two bits allow to select one of two special functions for the IOA and IOB registers. Then each pin in that IO register can be switched between normal GPIO and special function using the MASK register. 
-  * IOA11: FM + 
-  * IOA10: FP +For IOA, special = 0 selects the TFT display interface, special = 1 selects the STN LCD interface and I2S audio output. 
-  * IOA9: LP + 
-  * IOA8: CP +For IOB, only special = 0 is documented and it selects the CSB0, CSB1, CSB2 chip select pins for external memory (further configured by port 3D23) 
-  * IOA7-0D7-0 + 
-  * IOC15SPI clock +  * Bit 2IOA Wakeup enable 
-  * IOC14RX +  * Bit 3IOB Wakeup enable 
-  * IOC13: TX +  * Bit 4IOC Wakeup enable 
-  * IOC12: SPI SSB + 
-  * IOC11: TFT Clock +These bits enable system wakeup from sleep mode from activity on the corresponding IO ports. A typical setup on the V.Smile is to enable wakeup on port B to detect when the ON button is pressed. 
-  * IOC10: timebase +===== Input pins configuration ===== 
-  * IOC9: TAPWM + 
-  * IOC8: VSYNC +If the attribute bit for a pin is 0, the data bit can be used to set a pull up or pull down resistor on the pin. 
-  * IOC7: HSYNC + 
-  * IOC1: timebase 2 / external clock input +If the attribute bit is 1, the pin is floating without pull up or pull down. 
-  * IOC0: TBPWM / external clock 2 input+ 
 +It is possible to read both the internal buffer and the actual state of the pin. 
 + 
 +===== Output pins configuration ===== 
 + 
 +If the attribute bit for a pin is 0, the output is inverted. Writing to the data bit results in a logic 0 output. If the data bit is set to 0, the result is a logic 1 output. 
 + 
 +If the attribute bit is 1, there is no inversion, and the data bit is output as is.
  
  
Line 72: Line 79:
 | 3D1C   | Scanline counter         | | 3D1C   | Scanline counter         |
  
-Timebase values: +Timebase setup values: 
- +  * Bits 3-2: TMB2 frequency 
-  - 00: TMB2 = 128Hz, TMB1 = 8Hz +    * 00 128 Hz 
-  - 01: TMB2 = 256Hz, TMB1 = 16Hz +    * 01 - 256 Hz 
-  - 10TMB2 = 512Hz, TMB1 = 32Hz +    * 10 - 512 Hz 
-  - 11: TMB2 = 1024Hz, TMB1 = 64Hz+    * 11 - 1024 Hz 
 +  * Bits 1-0: TMB1 frequency 
 +    * 00 8 Hz 
 +    * 01 - 16 Hz 
 +    * 10 - 32 Hz 
 +    * 11 - 64 Hz
  
 ===== Timer A ===== ===== Timer A =====
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 | 3D2D   | Pseudo Random2                    | | 3D2D   | Pseudo Random2                    |
 | 3D2E   | FIQ Sel     | 3D2E   | FIQ Sel    
-| 3D2F    | DS register                            |+| 3D2F    | DS register (sets or gets data segment value of CPU status register) |
  
 ===== System control ===== ===== System control =====
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 | FFFD           | IRQ5  |External interrupts         | | FFFD           | IRQ5  |External interrupts         |
 | FFFE           | IRQ6  |1024, 2048 or 4096Hz ticker | | FFFE           | IRQ6  |1024, 2048 or 4096Hz ticker |
-| FFFF           | IRQ7  |4Hz ticker, TMB1TMB2LVD, Key change |+| FFFF           | IRQ7  |4Hz ticker, Timebase 1Timebase 2Low voltage detect, Key change |
  
 As the vector addresses are only 16-bit, they can only point to the first segment (0x0000 - 0xFFFF). As the vector addresses are only 16-bit, they can only point to the first segment (0x0000 - 0xFFFF).
 ===== External bus configuration ===== ===== External bus configuration =====
  
-   * Bits 11-8: Ram decode control +   * Bits 11-8: External RAM decode control 
-   * Bits 7-6: Address decode control +     * 0xxx - No mapping 
-   * Bits 5-3: Bus arbitration control+     * 1000 - Map ''0x3ff000 - 0x3fffff'' to RAMCSB (4 kibiwords) 
 +     * 1001 - Map ''0x3fe000 - 0x3fffff'' to RAMCSB (8 kibiwords) 
 +     * 1010 - Map ''0x3fc000 - 0x3fffff'' to RAMCSB (16 kibiwords) 
 +     * 1011 - Map ''0x3f8000 - 0x3fffff'' to RAMCSB (32 kibiwords) 
 +     * 1100 - Map ''0x3f0000 - 0x3fffff'' to RAMCSB (64 kibiwords) 
 +     * 1101 - Map ''0x3e0000 - 0x3fffff'' to RAMCSB (128 kibiwords) 
 +     * 1110 - Map ''0x3c0000 - 0x3fffff'' to RAMCSB (256 kibiwords) 
 +     * 1111 - Map ''0x380000 - 0x3fffff'' to RAMCSB (512 kibiwords) 
 +   * Bits 7-6: ROM address decode control 
 +     * 00 - Map entire range to ROMCSB  
 +     * 01 - Map ''0x4000 - 0x1fffff'' to ROMCSB, ''0x200000 - 0x3fffff'' to CSB1 
 +     * 1x - Map ''0x4000 - 0x0fffff'' to ROMCSB, ''0x100000 - 0x1fffff'' to CSB1, ''0x200000 - 0x2fffff'' to CSB2, ''0x300000 - 0x3fffff'' to CSB3 
 +   * Bits 5-3: Bus arbitration priority control 
 +     * 101 - 1. Audio, 2. PPU, 3. CPU 
 +     * 111 - 1. PPU, 2. Audio, 3. CPU
    * Bits 2-1: Number of wait states    * Bits 2-1: Number of wait states
    * Bit 0: CKOEN    * Bit 0: CKOEN
 +
 +External RAM mapping overrides any ROM mapping.
 +
 +On the V.Smile, both ROMCSB and CSB1 allow to access the cartridge ROM. This means bit 6 is not very useful.
 +
 +CSB2 is the cartridge RAM, and CSB3 is the system ROM. They are both enabled at the same time by using bit 7.
  
 ==== ADC ==== ==== ADC ====
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   * 115200: FF F1   * 115200: FF F1
  
 +Before using the UART, the corresponding PINs need to be configured properly. IOC13 and IOC14 must be set to "special"/"mask" mode to disable the GPIO and assign the pin to UART.
 +The example below also forces CTS A (IOC8) low, allowing the first controller port to transmit data. Normally this would only be done after receiving an RTS from said controller.
 +
 + // Enable controller CTS
 + *PORTC_DIR = 0x89c0;
 + *PORTC_ATTR = 0x89c0;
 + *PORTC_DATA = 0xf77f;
 +
 + // Enable Uart RX (controller input)
 + *UART_BAUDRATE_LOW = 0xA0;
 + *UART_BAUDRATE_HIGH = 0xFE;
 + *UART_CONTROL = 0xc3;
 + *UART_STATUS = 3;
 +
 + *PORTC_SPECIAL |= 0x6000; // UART Tx and Rx in "special" mode
 + *PORTC_ATTR |= 0x6000;
 + *PORTC_DIR |= 0x4000;
 +
 +Reading from the UART then is quite simple:
 +
 +  * Wait until the status register indicates Rx ready (bit 0)
 +  * When Rx is ready, read the Rx data register to get the byte
 +
 +For transmitting, you need to check if the FIFO is cleared (bit 1 of status register) then you can push your bytes to the transmit register.
 ====== SPI ====== ====== SPI ======
  
memory_map.1630006300.txt.gz · Last modified: 2021/08/26 21:31 by pulkomandy
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