Differences

This shows you the differences between two versions of the page.

--- memory_map [2021/09/21 21:53] – [IO special functions and usage] Removed incorrect data about io mappings. pulkomandy
+++ memory_map [2023/04/16 10:15] (current) – [External bus configuration] pulkomandy
@@ Line 31: / Line 31: @@
 The direction register is 0 for input pins, 1 for output pins.
+===== Global configuration register =====
+  * Bit 0: IOA special functions select
+  * Bit 1: IOB special functions select
+These two bits allow to select one of two special functions for the IOA and IOB registers. Then each pin in that IO register can be switched between normal GPIO and special function using the MASK register.
+For IOA, special = 0 selects the TFT display interface, special = 1 selects the STN LCD interface and I2S audio output.
+For IOB, only special = 0 is documented and it selects the CSB0, CSB1, CSB2 chip select pins for external memory (further configured by port 3D23)
+  * Bit 2: IOA Wakeup enable
+  * Bit 3: IOB Wakeup enable
+  * Bit 4: IOC Wakeup enable
+These bits enable system wakeup from sleep mode from activity on the corresponding IO ports. A typical setup on the V.Smile is to enable wakeup on port B to detect when the ON button is pressed.
 ===== Input pins configuration =====
@@ Line 198: / Line 214: @@
      * 00 - Map entire range to ROMCSB
      * 01 - Map ''0x4000 - 0x1fffff'' to ROMCSB, ''0x200000 - 0x3fffff'' to CSB1
-     * 1x - Map ''0x4000 - 0x0fffff'' to ROMCSB, ''0x100000 - 0x1fffff'' to CSB1, ''0x200000 - 0x2fffff'' to CSB2, ''0x300000 - 0x3fffff'' to CSB1
+     * 1x - Map ''0x4000 - 0x0fffff'' to ROMCSB, ''0x100000 - 0x1fffff'' to CSB1, ''0x200000 - 0x2fffff'' to CSB2, ''0x300000 - 0x3fffff'' to CSB3
    * Bits 5-3: Bus arbitration priority control
      * 101 - 1. Audio, 2. PPU, 3. CPU
@@ Line 206: / Line 222: @@
 External RAM mapping overrides any ROM mapping.
+On the V.Smile, both ROMCSB and CSB1 allow to access the cartridge ROM. This means bit 6 is not very useful.
+CSB2 is the cartridge RAM, and CSB3 is the system ROM. They are both enabled at the same time by using bit 7.
 ==== ADC ====
@@ Line 279: / Line 299: @@
   * 115200: FF F1
+Before using the UART, the corresponding PINs need to be configured properly. IOC13 and IOC14 must be set to "special"/"mask" mode to disable the GPIO and assign the pin to UART.
+The example below also forces CTS A (IOC8) low, allowing the first controller port to transmit data. Normally this would only be done after receiving an RTS from said controller.
+	// Enable controller CTS
+	*PORTC_DIR = 0x89c0;
+	*PORTC_ATTR = 0x89c0;
+	*PORTC_DATA = 0xf77f;
+	// Enable Uart RX (controller input)
+	*UART_BAUDRATE_LOW = 0xA0;
+	*UART_BAUDRATE_HIGH = 0xFE;
+	*UART_CONTROL = 0xc3;
+	*UART_STATUS = 3;
+	*PORTC_SPECIAL |= 0x6000; // UART Tx and Rx in "special" mode
+	*PORTC_ATTR |= 0x6000;
+	*PORTC_DIR |= 0x4000;
+Reading from the UART then is quite simple:
+  * Wait until the status register indicates Rx ready (bit 0)
+  * When Rx is ready, read the Rx data register to get the byte
+For transmitting, you need to check if the FIFO is cleared (bit 1 of status register) then you can push your bytes to the transmit register.
 ====== SPI ======